Migrate to Boost.Signals2 from Boost.Signals

Boost.Signals was deprecated and is not improved further. This patch removes Boost.Signals from 3rdParty and adds Boost.Signals2 and its dependencies. Also removed the Qt signals compatibility file Swiften/Base/boost_bsignals.h. Test-Information: Build and ran unit tests on OS X 10.11.4. Confirmed successful login using Swift client. Change-Id: Ie6e3b2d15aac2462cda95401582f5287a479fb54
author: Tobias Markmann <tm@ayena.de> 2016-04-05 13:17:19 (GMT)
committer: Tobias Markmann <tm@ayena.de> 2016-04-05 19:42:39 (GMT)
commit: 2b560b129b7a31fc8cc07f618e763c95a22bf832 (patch)
tree: 73e72cdc758b79d01485dc28dcedd48b26859ae8 /3rdParty/Boost/src/libs/atomic/doc
parent: 3c560e31b0f168da917e8d566db01fd1cd997d86 (diff)
download: swift-2b560b129b7a31fc8cc07f618e763c95a22bf832.zip
swift-2b560b129b7a31fc8cc07f618e763c95a22bf832.tar.bz2
7 files changed, 3164 insertions, 0 deletions
diff --git a/3rdParty/Boost/src/libs/atomic/doc/Jamfile.v2 b/3rdParty/Boost/src/libs/atomic/doc/Jamfile.v2
new file mode 100644
index 0000000..c293a66
--- /dev/null
+++ b/3rdParty/Boost/src/libs/atomic/doc/Jamfile.v2
@@ -0,0 +1,26 @@
+#  Boost.Atomic library documentation Jamfile
+#
+#  Copyright Helge Bahmann 2011.
+#  Copyright Tim Blechmann 2012.
+#  Distributed under the Boost Software License, Version 1.0.
+#     (See accompanying file LICENSE_1_0.txt or copy at
+#           http://www.boost.org/LICENSE_1_0.txt)
+
+import quickbook ;
+import boostbook : boostbook ;
+
+xml atomic : atomic.qbk ;
+
+boostbook standalone
+    : atomic
+    : <xsl:param>boost.root=../../../..
+      <xsl:param>boost.libraries=../../../libraries.htm
+      <format>pdf:<xsl:param>boost.url.prefix=http://www.boost.org/doc/libs/release/libs/atomic/doc/html
+    ;
+
+install css : [ glob $(BOOST_ROOT)/doc/src/*.css ]
+    : <location>html ;
+install images : [ glob $(BOOST_ROOT)/doc/src/images/*.png ]
+    : <location>html/images ;
+explicit css ;
+explicit images ;
diff --git a/3rdParty/Boost/src/libs/atomic/doc/atomic.hpp b/3rdParty/Boost/src/libs/atomic/doc/atomic.hpp
new file mode 100644
index 0000000..60e61c2
--- /dev/null
+++ b/3rdParty/Boost/src/libs/atomic/doc/atomic.hpp
@@ -0,0 +1,547 @@
+/** \file boost/atomic.hpp */
+
+//  Copyright (c) 2009 Helge Bahmann
+//
+//  Distributed under the Boost Software License, Version 1.0.
+//  See accompanying file LICENSE_1_0.txt or copy at
+//  http://www.boost.org/LICENSE_1_0.txt)
+
+/* this is just a pseudo-header file fed to doxygen
+to more easily generate the class documentation; will
+be replaced by proper documentation down the road */
+
+namespace boost {
+
+/**
+    \brief Memory ordering constraints
+
+    This defines the relative order of one atomic operation
+    and other memory operations (loads, stores, other atomic operations)
+    executed by the same thread.
+
+    The order of operations specified by the programmer in the
+    source code ("program order") does not necessarily match
+    the order in which they are actually executed on the target system:
+    Both compiler as well as processor may reorder operations
+    quite arbitrarily. <B>Specifying the wrong ordering
+    constraint will therefore generally result in an incorrect program.</B>
+*/
+enum memory_order {
+    /**
+        \brief No constraint
+        Atomic operation and other memory operations may be reordered freely.
+    */
+    memory_order_relaxed,
+    /**
+        \brief Data dependence constraint
+        Atomic operation must strictly precede any memory operation that
+        computationally depends on the outcome of the atomic operation.
+    */
+    memory_order_consume,
+    /**
+        \brief Acquire memory
+        Atomic operation must strictly precede all memory operations that
+        follow in program order.
+    */
+    memory_order_acquire,
+    /**
+        \brief Release memory
+        Atomic operation must strictly follow all memory operations that precede
+        in program order.
+    */
+    memory_order_release,
+    /**
+        \brief Acquire and release memory
+        Combines the effects of \ref memory_order_acquire and \ref memory_order_release
+    */
+    memory_order_acq_rel,
+    /**
+        \brief Sequentially consistent
+        Produces the same result \ref memory_order_acq_rel, but additionally
+        enforces globally sequential consistent execution
+    */
+    memory_order_seq_cst
+};
+
+/**
+    \brief Atomic datatype
+
+    An atomic variable. Provides methods to modify this variable atomically.
+    Valid template parameters are:
+
+    - integral data types (char, short, int, ...)
+    - pointer data types
+    - any other data type that has a non-throwing default
+      constructor and that can be copied via <TT>memcpy</TT>
+
+    Unless specified otherwise, any memory ordering constraint can be used
+    with any of the atomic operations.
+*/
+template<typename Type>
+class atomic {
+public:
+    /**
+        \brief Create uninitialized atomic variable
+        Creates an atomic variable. Its initial value is undefined.
+    */
+    atomic();
+    /**
+        \brief Create an initialize atomic variable
+        \param value Initial value
+        Creates and initializes an atomic variable.
+    */
+    explicit atomic(Type value);
+
+    /**
+        \brief Read the current value of the atomic variable
+        \param order Memory ordering constraint, see \ref memory_order
+        \return Current value of the variable
+
+        Valid memory ordering constraints are:
+        - @c memory_order_relaxed
+        - @c memory_order_consume
+        - @c memory_order_acquire
+        - @c memory_order_seq_cst
+    */
+    Type load(memory_order order=memory_order_seq_cst) const;
+
+    /**
+        \brief Write new value to atomic variable
+        \param value New value
+        \param order Memory ordering constraint, see \ref memory_order
+
+        Valid memory ordering constraints are:
+        - @c memory_order_relaxed
+        - @c memory_order_release
+        - @c memory_order_seq_cst
+    */
+    void store(Type value, memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Atomically compare and exchange variable
+        \param expected Expected old value
+        \param desired Desired new value
+        \param order Memory ordering constraint, see \ref memory_order
+        \return @c true if value was changed
+
+        Atomically performs the following operation
+
+        \code
+        if (variable==expected) {
+            variable=desired;
+            return true;
+        } else {
+            expected=variable;
+            return false;
+        }
+        \endcode
+
+        This operation may fail "spuriously", i.e. the state of the variable
+        is unchanged even though the expected value was found (this is the
+        case on architectures using "load-linked"/"store conditional" to
+        implement the operation).
+
+        The established memory order will be @c order if the operation
+        is successful. If the operation is unsuccessful, the
+        memory order will be
+
+        - @c memory_order_relaxed if @c order is @c memory_order_acquire ,
+          @c memory_order_relaxed or @c memory_order_consume
+        - @c memory_order_release if @c order is @c memory_order_acq_release
+          or @c memory_order_release
+        - @c memory_order_seq_cst if @c order is @c memory_order_seq_cst
+    */
+    bool compare_exchange_weak(
+        Type &expected,
+        Type desired,
+        memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Atomically compare and exchange variable
+        \param expected Expected old value
+        \param desired Desired new value
+        \param success_order Memory ordering constraint if operation
+        is successful
+        \param failure_order Memory ordering constraint if operation is unsuccessful
+        \return @c true if value was changed
+
+        Atomically performs the following operation
+
+        \code
+        if (variable==expected) {
+            variable=desired;
+            return true;
+        } else {
+            expected=variable;
+            return false;
+        }
+        \endcode
+
+        This operation may fail "spuriously", i.e. the state of the variable
+        is unchanged even though the expected value was found (this is the
+        case on architectures using "load-linked"/"store conditional" to
+        implement the operation).
+
+        The constraint imposed by @c success_order may not be
+        weaker than the constraint imposed by @c failure_order.
+    */
+    bool compare_exchange_weak(
+        Type &expected,
+        Type desired,
+        memory_order success_order,
+        memory_order failure_order);
+    /**
+        \brief Atomically compare and exchange variable
+        \param expected Expected old value
+        \param desired Desired new value
+        \param order Memory ordering constraint, see \ref memory_order
+        \return @c true if value was changed
+
+        Atomically performs the following operation
+
+        \code
+        if (variable==expected) {
+            variable=desired;
+            return true;
+        } else {
+            expected=variable;
+            return false;
+        }
+        \endcode
+
+        In contrast to \ref compare_exchange_weak, this operation will never
+        fail spuriously. Since compare-and-swap must generally be retried
+        in a loop, implementors are advised to prefer \ref compare_exchange_weak
+        where feasible.
+
+        The established memory order will be @c order if the operation
+        is successful. If the operation is unsuccessful, the
+        memory order will be
+
+        - @c memory_order_relaxed if @c order is @c memory_order_acquire ,
+          @c memory_order_relaxed or @c memory_order_consume
+        - @c memory_order_release if @c order is @c memory_order_acq_release
+          or @c memory_order_release
+        - @c memory_order_seq_cst if @c order is @c memory_order_seq_cst
+    */
+    bool compare_exchange_strong(
+        Type &expected,
+        Type desired,
+        memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Atomically compare and exchange variable
+        \param expected Expected old value
+        \param desired Desired new value
+        \param success_order Memory ordering constraint if operation
+        is successful
+        \param failure_order Memory ordering constraint if operation is unsuccessful
+        \return @c true if value was changed
+
+        Atomically performs the following operation
+
+        \code
+        if (variable==expected) {
+            variable=desired;
+            return true;
+        } else {
+            expected=variable;
+            return false;
+        }
+        \endcode
+
+        In contrast to \ref compare_exchange_weak, this operation will never
+        fail spuriously. Since compare-and-swap must generally be retried
+        in a loop, implementors are advised to prefer \ref compare_exchange_weak
+        where feasible.
+
+        The constraint imposed by @c success_order may not be
+        weaker than the constraint imposed by @c failure_order.
+    */
+    bool compare_exchange_strong(
+        Type &expected,
+        Type desired,
+        memory_order success_order,
+        memory_order failure_order);
+    /**
+        \brief Atomically exchange variable
+        \param value New value
+        \param order Memory ordering constraint, see \ref memory_order
+        \return Old value of the variable
+
+        Atomically exchanges the value of the variable with the new
+        value and returns its old value.
+    */
+    Type exchange(Type value, memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Atomically add and return old value
+        \param operand Operand
+        \param order Memory ordering constraint, see \ref memory_order
+        \return Old value of the variable
+
+        Atomically adds operand to the variable and returns its
+        old value.
+    */
+    Type fetch_add(Type operand, memory_order order=memory_order_seq_cst);
+    /**
+        \brief Atomically subtract and return old value
+        \param operand Operand
+        \param order Memory ordering constraint, see \ref memory_order
+        \return Old value of the variable
+
+        Atomically subtracts operand from the variable and returns its
+        old value.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        @c operand is of type @c ptrdiff_t and the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type fetch_sub(Type operand, memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Atomically perform bitwise "AND" and return old value
+        \param operand Operand
+        \param order Memory ordering constraint, see \ref memory_order
+        \return Old value of the variable
+
+        Atomically performs bitwise "AND" with the variable and returns its
+        old value.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        @c operand is of type @c ptrdiff_t and the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type fetch_and(Type operand, memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Atomically perform bitwise "OR" and return old value
+        \param operand Operand
+        \param order Memory ordering constraint, see \ref memory_order
+        \return Old value of the variable
+
+        Atomically performs bitwise "OR" with the variable and returns its
+        old value.
+
+        This method is available only if \c Type is an integral type.
+    */
+    Type fetch_or(Type operand, memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Atomically perform bitwise "XOR" and return old value
+        \param operand Operand
+        \param order Memory ordering constraint, see \ref memory_order
+        \return Old value of the variable
+
+        Atomically performs bitwise "XOR" with the variable and returns its
+        old value.
+
+        This method is available only if \c Type is an integral type.
+    */
+    Type fetch_xor(Type operand, memory_order order=memory_order_seq_cst);
+
+    /**
+        \brief Implicit load
+        \return Current value of the variable
+
+        The same as <tt>load(memory_order_seq_cst)</tt>. Avoid using
+        the implicit conversion operator, use \ref load with
+        an explicit memory ordering constraint.
+    */
+    operator Type(void) const;
+    /**
+        \brief Implicit store
+        \param value New value
+        \return Copy of @c value
+
+        The same as <tt>store(value, memory_order_seq_cst)</tt>. Avoid using
+        the implicit conversion operator, use \ref store with
+        an explicit memory ordering constraint.
+    */
+    Type operator=(Type v);
+
+    /**
+        \brief Atomically perform bitwise "AND" and return new value
+        \param operand Operand
+        \return New value of the variable
+
+        The same as <tt>fetch_and(operand, memory_order_seq_cst)&operand</tt>.
+        Avoid using the implicit bitwise "AND" operator, use \ref fetch_and
+        with an explicit memory ordering constraint.
+    */
+    Type operator&=(Type operand);
+
+    /**
+        \brief Atomically perform bitwise "OR" and return new value
+        \param operand Operand
+        \return New value of the variable
+
+        The same as <tt>fetch_or(operand, memory_order_seq_cst)|operand</tt>.
+        Avoid using the implicit bitwise "OR" operator, use \ref fetch_or
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type.
+    */
+    Type operator|=(Type operand);
+
+    /**
+        \brief Atomically perform bitwise "XOR" and return new value
+        \param operand Operand
+        \return New value of the variable
+
+        The same as <tt>fetch_xor(operand, memory_order_seq_cst)^operand</tt>.
+        Avoid using the implicit bitwise "XOR" operator, use \ref fetch_xor
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type.
+    */
+    Type operator^=(Type operand);
+
+    /**
+        \brief Atomically add and return new value
+        \param operand Operand
+        \return New value of the variable
+
+        The same as <tt>fetch_add(operand, memory_order_seq_cst)+operand</tt>.
+        Avoid using the implicit add operator, use \ref fetch_add
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        @c operand is of type @c ptrdiff_t and the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type operator+=(Type operand);
+
+    /**
+        \brief Atomically subtract and return new value
+        \param operand Operand
+        \return New value of the variable
+
+        The same as <tt>fetch_sub(operand, memory_order_seq_cst)-operand</tt>.
+        Avoid using the implicit subtract operator, use \ref fetch_sub
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        @c operand is of type @c ptrdiff_t and the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type operator-=(Type operand);
+
+    /**
+        \brief Atomically increment and return new value
+        \return New value of the variable
+
+        The same as <tt>fetch_add(1, memory_order_seq_cst)+1</tt>.
+        Avoid using the implicit increment operator, use \ref fetch_add
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type operator++(void);
+    /**
+        \brief Atomically increment and return old value
+        \return Old value of the variable
+
+        The same as <tt>fetch_add(1, memory_order_seq_cst)</tt>.
+        Avoid using the implicit increment operator, use \ref fetch_add
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type operator++(int);
+    /**
+        \brief Atomically subtract and return new value
+        \return New value of the variable
+
+        The same as <tt>fetch_sub(1, memory_order_seq_cst)-1</tt>.
+        Avoid using the implicit increment operator, use \ref fetch_sub
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type operator--(void);
+    /**
+        \brief Atomically subtract and return old value
+        \return Old value of the variable
+
+        The same as <tt>fetch_sub(1, memory_order_seq_cst)</tt>.
+        Avoid using the implicit increment operator, use \ref fetch_sub
+        with an explicit memory ordering constraint.
+
+        This method is available only if \c Type is an integral type
+        or a non-void pointer type. If it is a pointer type,
+        the operation
+        is performed following the rules for pointer arithmetic
+        in C++.
+    */
+    Type operator--(int);
+
+    /** \brief Deleted copy constructor */
+    atomic(const atomic &) = delete;
+    /** \brief Deleted copy assignment */
+    const atomic & operator=(const atomic &) = delete;
+};
+
+/**
+    \brief Insert explicit fence for thread synchronization
+    \param order Memory ordering constraint
+
+    Inserts an explicit fence. The exact semantic depends on the
+    type of fence inserted:
+
+    - \c memory_order_relaxed: No operation
+    - \c memory_order_release: Performs a "release" operation
+    - \c memory_order_acquire or \c memory_order_consume: Performs an
+      "acquire" operation
+    - \c memory_order_acq_rel: Performs both an "acquire" and a "release"
+      operation
+    - \c memory_order_seq_cst: Performs both an "acquire" and a "release"
+      operation and in addition there exists a global total order of
+      all \c memory_order_seq_cst operations
+
+*/
+void atomic_thread_fence(memory_order order);
+
+/**
+    \brief Insert explicit fence for synchronization with a signal handler
+    \param order Memory ordering constraint
+
+    Inserts an explicit fence to synchronize with a signal handler called within
+    the context of the same thread. The fence ensures the corresponding operations
+    around it are complete and/or not started. The exact semantic depends on the
+    type of fence inserted:
+
+    - \c memory_order_relaxed: No operation
+    - \c memory_order_release: Ensures the operations before the fence are complete
+    - \c memory_order_acquire or \c memory_order_consume: Ensures the operations
+         after the fence are not started.
+    - \c memory_order_acq_rel or \c memory_order_seq_cst: Ensures the operations
+      around the fence do not cross it.
+
+    Note that this call does not affect visibility order of the memory operations
+    to other threads. It is functionally similar to \c atomic_thread_fence, only
+    it does not generate any instructions to synchronize hardware threads.
+*/
+void atomic_signal_fence(memory_order order);
+
+}
diff --git a/3rdParty/Boost/src/libs/atomic/doc/atomic.qbk b/3rdParty/Boost/src/libs/atomic/doc/atomic.qbk
new file mode 100644
index 0000000..880fab5
--- /dev/null
+++ b/3rdParty/Boost/src/libs/atomic/doc/atomic.qbk
@@ -0,0 +1,828 @@
+[/
+ / Copyright (c) 2009 Helge Bahmann
+ / Copyright (c) 2014 Andrey Semashev
+ /
+ / Distributed under the Boost Software License, Version 1.0. (See accompanying
+ / file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
+ /]
+
+[library Boost.Atomic
+    [quickbook 1.4]
+    [authors [Bahmann, Helge][Semashev, Andrey]]
+    [copyright 2011 Helge Bahmann]
+    [copyright 2012 Tim Blechmann]
+    [copyright 2013 Andrey Semashev]
+    [id atomic]
+    [dirname atomic]
+    [purpose Atomic operations]
+    [license
+        Distributed under the Boost Software License, Version 1.0.
+        (See accompanying file LICENSE_1_0.txt or copy at
+        [@http://www.boost.org/LICENSE_1_0.txt])
+    ]
+]
+
+[section:introduction Introduction]
+
+[section:introduction_presenting Presenting Boost.Atomic]
+
+[*Boost.Atomic] is a library that provides [^atomic]
+data types and operations on these data types, as well as memory
+ordering constraints required for coordinating multiple threads through
+atomic variables. It implements the interface as defined by the C++11
+standard, but makes this feature available for platforms lacking
+system/compiler support for this particular C++11 feature.
+
+Users of this library should already be familiar with concurrency
+in general, as well as elementary concepts such as "mutual exclusion".
+
+The implementation makes use of processor-specific instructions where
+possible (via inline assembler, platform libraries or compiler
+intrinsics), and falls back to "emulating" atomic operations through
+locking.
+
+[endsect]
+
+[section:introduction_purpose Purpose]
+
+Operations on "ordinary" variables are not guaranteed to be atomic.
+This means that with [^int n=0] initially, two threads concurrently
+executing
+
+[c++]
+
+  void function()
+  {
+    n ++;
+  }
+
+might result in [^n==1] instead of 2: Each thread will read the
+old value into a processor register, increment it and write the result
+back. Both threads may therefore write [^1], unaware that the other thread
+is doing likewise.
+
+Declaring [^atomic<int> n=0] instead, the same operation on
+this variable will always result in [^n==2] as each operation on this
+variable is ['atomic]: This means that each operation behaves as if it
+were strictly sequentialized with respect to the other.
+
+Atomic variables are useful for two purposes:
+
+* as a means for coordinating multiple threads via custom
+  coordination protocols
+* as faster alternatives to "locked" access to simple variables
+
+Take a look at the [link atomic.usage_examples examples] section
+for common patterns.
+
+[endsect]
+
+[endsect]
+
+[section:thread_coordination Thread coordination using Boost.Atomic]
+
+The most common use of [*Boost.Atomic] is to realize custom
+thread synchronization protocols: The goal is to coordinate
+accesses of threads to shared variables in order to avoid
+"conflicts". The
+programmer must be aware of the fact that
+compilers, CPUs and the cache
+hierarchies may generally reorder memory references at will.
+As a consequence a program such as:
+
+[c++]
+
+  int x = 0, int y = 0;
+
+  thread1:
+    x = 1;
+    y = 1;
+
+  thread2
+    if (y == 1) {
+      assert(x == 1);
+    }
+
+might indeed fail as there is no guarantee that the read of `x`
+by thread2 "sees" the write by thread1.
+
+[*Boost.Atomic] uses a synchronisation concept based on the
+['happens-before] relation to describe the guarantees under
+which situations such as the above one cannot occur.
+
+The remainder of this section will discuss ['happens-before] in
+a "hands-on" way instead of giving a fully formalized definition.
+The reader is encouraged to additionally have a
+look at the discussion of the correctness of a few of the
+[link atomic.usage_examples examples] afterwards.
+
+[section:mutex Enforcing ['happens-before] through mutual exclusion]
+
+As an introductory example to understand how arguing using
+['happens-before] works, consider two threads synchronizing
+using a common mutex:
+
+[c++]
+
+  mutex m;
+
+  thread1:
+    m.lock();
+    ... /* A */
+    m.unlock();
+
+  thread2:
+    m.lock();
+    ... /* B */
+    m.unlock();
+
+The "lockset-based intuition" would be to argue that A and B
+cannot be executed concurrently as the code paths require a
+common lock to be held.
+
+One can however also arrive at the same conclusion using
+['happens-before]: Either thread1 or thread2 will succeed first
+at [^m.lock()]. If this is be thread1, then as a consequence,
+thread2 cannot succeed at [^m.lock()] before thread1 has executed
+[^m.unlock()], consequently A ['happens-before] B in this case.
+By symmetry, if thread2 succeeds at [^m.lock()] first, we can
+conclude B ['happens-before] A.
+
+Since this already exhausts all options, we can conclude that
+either A ['happens-before] B or B ['happens-before] A must
+always hold. Obviously cannot state ['which] of the two relationships
+holds, but either one is sufficient to conclude that A and B
+cannot conflict.
+
+Compare the [link boost_atomic.usage_examples.example_spinlock spinlock]
+implementation to see how the mutual exclusion concept can be
+mapped to [*Boost.Atomic].
+
+[endsect]
+
+[section:release_acquire ['happens-before] through [^release] and [^acquire]]
+
+The most basic pattern for coordinating threads via [*Boost.Atomic]
+uses [^release] and [^acquire] on an atomic variable for coordination: If ...
+
+* ... thread1 performs an operation A,
+* ... thread1 subsequently writes (or atomically
+  modifies) an atomic variable with [^release] semantic,
+* ... thread2 reads (or atomically reads-and-modifies)
+  the value this value from the same atomic variable with
+  [^acquire] semantic and
+* ... thread2 subsequently performs an operation B,
+
+... then A ['happens-before] B.
+
+Consider the following example
+
+[c++]
+
+  atomic<int> a(0);
+
+  thread1:
+    ... /* A */
+    a.fetch_add(1, memory_order_release);
+
+  thread2:
+    int tmp = a.load(memory_order_acquire);
+    if (tmp == 1) {
+      ... /* B */
+    } else {
+      ... /* C */
+    }
+
+In this example, two avenues for execution are possible:
+
+* The [^store] operation by thread1 precedes the [^load] by thread2:
+  In this case thread2 will execute B and "A ['happens-before] B"
+  holds as all of the criteria above are satisfied.
+* The [^load] operation by thread2 precedes the [^store] by thread1:
+  In this case, thread2 will execute C, but "A ['happens-before] C"
+  does ['not] hold: thread2 does not read the value written by
+  thread1 through [^a].
+
+Therefore, A and B cannot conflict, but A and C ['can] conflict.
+
+[endsect]
+
+[section:fences Fences]
+
+Ordering constraints are generally specified together with an access to
+an atomic variable. It is however also possible to issue "fence"
+operations in isolation, in this case the fence operates in
+conjunction with preceding (for `acquire`, `consume` or `seq_cst`
+operations) or succeeding (for `release` or `seq_cst`) atomic
+operations.
+
+The example from the previous section could also be written in
+the following way:
+
+[c++]
+
+  atomic<int> a(0);
+
+  thread1:
+    ... /* A */
+    atomic_thread_fence(memory_order_release);
+    a.fetch_add(1, memory_order_relaxed);
+
+  thread2:
+    int tmp = a.load(memory_order_relaxed);
+    if (tmp == 1) {
+      atomic_thread_fence(memory_order_acquire);
+      ... /* B */
+    } else {
+      ... /* C */
+    }
+
+This provides the same ordering guarantees as previously, but
+elides a (possibly expensive) memory ordering operation in
+the case C is executed.
+
+[endsect]
+
+[section:release_consume ['happens-before] through [^release] and [^consume]]
+
+The second pattern for coordinating threads via [*Boost.Atomic]
+uses [^release] and [^consume] on an atomic variable for coordination: If ...
+
+* ... thread1 performs an operation A,
+* ... thread1 subsequently writes (or atomically modifies) an
+  atomic variable with [^release] semantic,
+* ... thread2 reads (or atomically reads-and-modifies)
+  the value this value from the same atomic variable with [^consume] semantic and
+* ... thread2 subsequently performs an operation B that is ['computationally
+  dependent on the value of the atomic variable],
+
+... then A ['happens-before] B.
+
+Consider the following example
+
+[c++]
+
+  atomic<int> a(0);
+  complex_data_structure data[2];
+
+  thread1:
+    data[1] = ...; /* A */
+    a.store(1, memory_order_release);
+
+  thread2:
+    int index = a.load(memory_order_consume);
+    complex_data_structure tmp = data[index]; /* B */
+
+In this example, two avenues for execution are possible:
+
+* The [^store] operation by thread1 precedes the [^load] by thread2:
+  In this case thread2 will read [^data\[1\]] and "A ['happens-before] B"
+  holds as all of the criteria above are satisfied.
+* The [^load] operation by thread2 precedes the [^store] by thread1:
+  In this case thread2 will read [^data\[0\]] and "A ['happens-before] B"
+  does ['not] hold: thread2 does not read the value written by
+  thread1 through [^a].
+
+Here, the ['happens-before] relationship helps ensure that any
+accesses (presumable writes) to [^data\[1\]] by thread1 happen before
+before the accesses (presumably reads) to [^data\[1\]] by thread2:
+Lacking this relationship, thread2 might see stale/inconsistent
+data.
+
+Note that in this example, the fact that operation B is computationally
+dependent on the atomic variable, therefore the following program would
+be erroneous:
+
+[c++]
+
+  atomic<int> a(0);
+  complex_data_structure data[2];
+
+  thread1:
+    data[1] = ...; /* A */
+    a.store(1, memory_order_release);
+
+  thread2:
+    int index = a.load(memory_order_consume);
+    complex_data_structure tmp;
+    if (index == 0)
+      tmp = data[0];
+    else
+      tmp = data[1];
+
+[^consume] is most commonly (and most safely! see
+[link atomic.limitations limitations]) used with
+pointers, compare for example the
+[link boost_atomic.usage_examples.singleton singleton with double-checked locking].
+
+[endsect]
+
+[section:seq_cst Sequential consistency]
+
+The third pattern for coordinating threads via [*Boost.Atomic]
+uses [^seq_cst] for coordination: If ...
+
+* ... thread1 performs an operation A,
+* ... thread1 subsequently performs any operation with [^seq_cst],
+* ... thread1 subsequently performs an operation B,
+* ... thread2 performs an operation C,
+* ... thread2 subsequently performs any operation with [^seq_cst],
+* ... thread2 subsequently performs an operation D,
+
+then either "A ['happens-before] D" or "C ['happens-before] B" holds.
+
+In this case it does not matter whether thread1 and thread2 operate
+on the same or different atomic variables, or use a "stand-alone"
+[^atomic_thread_fence] operation.
+
+[endsect]
+
+[endsect]
+
+[section:interface Programming interfaces]
+
+[section:configuration Configuration and building]
+
+The library contains header-only and compiled parts. The library is
+header-only for lock-free cases but requires a separate binary to
+implement the lock-based emulation. Users are able to detect whether
+linking to the compiled part is required by checking the
+[link atomic.interface.feature_macros feature macros].
+
+The following macros affect library behavior:
+
+[table
+    [[Macro] [Description]]
+    [[`BOOST_ATOMIC_NO_CMPXCHG16B`] [Affects 64-bit x86 MSVC builds. When defined,
+      the library assumes the target CPU does not support `cmpxchg16b` instruction used
+      to support 128-bit atomic operations. This is the case with some early 64-bit AMD CPUs,
+      all Intel CPUs and current AMD CPUs support this instruction. The library does not
+      perform runtime detection of this instruction, so running the code that uses 128-bit
+      atomics on such CPUs will result in crashes, unless this macro is defined. Note that
+      the macro does not affect GCC and compatible compilers because the library infers
+      this information from the compiler-defined macros.]]
+    [[`BOOST_ATOMIC_FORCE_FALLBACK`] [When defined, all operations are implemented with locks.
+      This is mostly used for testing and should not be used in real world projects.]]
+    [[`BOOST_ATOMIC_DYN_LINK` and `BOOST_ALL_DYN_LINK`] [Control library linking. If defined,
+      the library assumes dynamic linking, otherwise static. The latter macro affects all Boost
+      libraries, not just [*Boost.Atomic].]]
+    [[`BOOST_ATOMIC_NO_LIB` and `BOOST_ALL_NO_LIB`] [Control library auto-linking on Windows.
+      When defined, disables auto-linking. The latter macro affects all Boost libraries,
+      not just [*Boost.Atomic].]]
+]
+
+Besides macros, it is important to specify the correct compiler options for the target CPU.
+With GCC and compatible compilers this affects whether particular atomic operations are
+lock-free or not.
+
+Boost building process is described in the [@http://www.boost.org/doc/libs/release/more/getting_started/ Getting Started guide].
+For example, you can build [*Boost.Atomic] with the following command line:
+
+[pre
+    bjam --with-atomic variant=release instruction-set=core2 stage
+]
+
+[endsect]
+
+[section:interface_memory_order Memory order]
+
+    #include <boost/memory_order.hpp>
+
+The enumeration [^boost::memory_order] defines the following
+values to represent memory ordering constraints:
+
+[table
+    [[Constant] [Description]]
+    [[`memory_order_relaxed`] [No ordering constraint.
+      Informally speaking, following operations may be reordered before,
+      preceding operations may be reordered after the atomic
+      operation. This constraint is suitable only when
+      either a) further operations do not depend on the outcome
+      of the atomic operation or b) ordering is enforced through
+      stand-alone `atomic_thread_fence` operations. The operation on
+      the atomic value itself is still atomic though.
+    ]]
+    [[`memory_order_release`] [
+      Perform `release` operation. Informally speaking,
+      prevents all preceding memory operations to be reordered
+      past this point.
+    ]]
+    [[`memory_order_acquire`] [
+      Perform `acquire` operation. Informally speaking,
+      prevents succeeding memory operations to be reordered
+      before this point.
+    ]]
+    [[`memory_order_consume`] [
+      Perform `consume` operation. More relaxed (and
+      on some architectures more efficient) than `memory_order_acquire`
+      as it only affects succeeding operations that are
+      computationally-dependent on the value retrieved from
+      an atomic variable.
+    ]]
+    [[`memory_order_acq_rel`] [Perform both `release` and `acquire` operation]]
+    [[`memory_order_seq_cst`] [
+      Enforce sequential consistency. Implies `memory_order_acq_rel`, but
+      additionally enforces total order for all operations such qualified.
+    ]]
+]
+
+See section [link atomic.thread_coordination ['happens-before]] for explanation
+of the various ordering constraints.
+
+[endsect]
+
+[section:interface_atomic_object Atomic objects]
+
+    #include <boost/atomic/atomic.hpp>
+
+[^boost::atomic<['T]>] provides methods for atomically accessing
+variables of a suitable type [^['T]]. The type is suitable if
+it is /trivially copyable/ (3.9/9 \[basic.types\]). Following are
+examples of the types compatible with this requirement:
+
+* a scalar type (e.g. integer, boolean, enum or pointer type)
+* a [^class] or [^struct] that has no non-trivial copy or move
+  constructors or assignment operators, has a trivial destructor,
+  and that is comparable via [^memcmp].
+
+Note that classes with virtual functions or virtual base classes
+do not satisfy the requirements. Also be warned
+that structures with "padding" between data members may compare
+non-equal via [^memcmp] even though all members are equal.
+
+[section:interface_atomic_generic [^boost::atomic<['T]>] template class]
+
+All atomic objects supports the following operations:
+
+[table
+    [[Syntax] [Description]]
+    [
+      [`atomic()`]
+      [Initialize to an unspecified value]
+    ]
+    [
+      [`atomic(T initial_value)`]
+      [Initialize to [^initial_value]]
+    ]
+    [
+      [`bool is_lock_free()`]
+      [Checks if the atomic object is lock-free]
+    ]
+    [
+      [`T load(memory_order order)`]
+      [Return current value]
+    ]
+    [
+      [`void store(T value, memory_order order)`]
+      [Write new value to atomic variable]
+    ]
+    [
+      [`T exchange(T new_value, memory_order order)`]
+      [Exchange current value with `new_value`, returning current value]
+    ]
+    [
+      [`bool compare_exchange_weak(T & expected, T desired, memory_order order)`]
+      [Compare current value with `expected`, change it to `desired` if matches.
+      Returns `true` if an exchange has been performed, and always writes the
+      previous value back in `expected`. May fail spuriously, so must generally be
+      retried in a loop.]
+    ]
+    [
+      [`bool compare_exchange_weak(T & expected, T desired, memory_order success_order, memory_order failure_order)`]
+      [Compare current value with `expected`, change it to `desired` if matches.
+      Returns `true` if an exchange has been performed, and always writes the
+      previous value back in `expected`. May fail spuriously, so must generally be
+      retried in a loop.]
+    ]
+    [
+      [`bool compare_exchange_strong(T & expected, T desired, memory_order order)`]
+      [Compare current value with `expected`, change it to `desired` if matches.
+      Returns `true` if an exchange has been performed, and always writes the
+      previous value back in `expected`.]
+    ]
+    [
+      [`bool compare_exchange_strong(T & expected, T desired, memory_order success_order, memory_order failure_order))`]
+      [Compare current value with `expected`, change it to `desired` if matches.
+      Returns `true` if an exchange has been performed, and always writes the
+      previous value back in `expected`.]
+    ]
+]
+
+`order` always has `memory_order_seq_cst` as default parameter.
+
+The `compare_exchange_weak`/`compare_exchange_strong` variants
+taking four parameters differ from the three parameter variants
+in that they allow a different memory ordering constraint to
+be specified in case the operation fails.
+
+In addition to these explicit operations, each
+[^atomic<['T]>] object also supports
+implicit [^store] and [^load] through the use of "assignment"
+and "conversion to [^T]" operators. Avoid using these operators,
+as they do not allow explicit specification of a memory ordering
+constraint.
+
+[endsect]
+
+[section:interface_atomic_integral [^boost::atomic<['integral]>] template class]
+
+In addition to the operations listed in the previous section,
+[^boost::atomic<['I]>] for integral
+types [^['I]] supports the following operations:
+
+[table
+    [[Syntax] [Description]]
+    [
+      [`T fetch_add(T v, memory_order order)`]
+      [Add `v` to variable, returning previous value]
+    ]
+    [
+      [`T fetch_sub(T v, memory_order order)`]
+      [Subtract `v` from variable, returning previous value]
+    ]
+    [
+      [`T fetch_and(T v, memory_order order)`]
+      [Apply bit-wise "and" with `v` to variable, returning previous value]
+    ]
+    [
+      [`T fetch_or(T v, memory_order order)`]
+      [Apply bit-wise "or" with `v` to variable, returning previous value]
+    ]
+    [
+      [`T fetch_xor(T v, memory_order order)`]
+      [Apply bit-wise "xor" with `v` to variable, returning previous value]
+    ]
+]
+
+`order` always has `memory_order_seq_cst` as default parameter.
+
+In addition to these explicit operations, each
+[^boost::atomic<['I]>] object also
+supports implicit pre-/post- increment/decrement, as well
+as the operators `+=`, `-=`, `&=`, `|=` and `^=`.
+Avoid using these operators,
+as they do not allow explicit specification of a memory ordering
+constraint.
+
+[endsect]
+
+[section:interface_atomic_pointer [^boost::atomic<['pointer]>] template class]
+
+In addition to the operations applicable to all atomic object,
+[^boost::atomic<['P]>] for pointer
+types [^['P]] (other than [^void] pointers) support the following operations:
+
+[table
+    [[Syntax] [Description]]
+    [
+      [`T fetch_add(ptrdiff_t v, memory_order order)`]
+      [Add `v` to variable, returning previous value]
+    ]
+    [
+      [`T fetch_sub(ptrdiff_t v, memory_order order)`]
+      [Subtract `v` from variable, returning previous value]
+    ]
+]
+
+`order` always has `memory_order_seq_cst` as default parameter.
+
+In addition to these explicit operations, each
+[^boost::atomic<['P]>] object also
+supports implicit pre-/post- increment/decrement, as well
+as the operators `+=`, `-=`. Avoid using these operators,
+as they do not allow explicit specification of a memory ordering
+constraint.
+
+[endsect]
+
+[endsect]
+
+[section:interface_fences Fences]
+
+    #include <boost/atomic/fences.hpp>
+
+[table
+    [[Syntax] [Description]]
+    [
+      [`void atomic_thread_fence(memory_order order)`]
+      [Issue fence for coordination with other threads.]
+    ]
+    [
+      [`void atomic_signal_fence(memory_order order)`]
+      [Issue fence for coordination with signal handler (only in same thread).]
+    ]
+]
+
+[endsect]
+
+[section:feature_macros Feature testing macros]
+
+    #include <boost/atomic/capabilities.hpp>
+
+[*Boost.Atomic] defines a number of macros to allow compile-time
+detection whether an atomic data type is implemented using
+"true" atomic operations, or whether an internal "lock" is
+used to provide atomicity. The following macros will be
+defined to `0` if operations on the data type always
+require a lock, to `1` if operations on the data type may
+sometimes require a lock, and to `2` if they are always lock-free:
+
+[table
+    [[Macro] [Description]]
+    [
+      [`BOOST_ATOMIC_FLAG_LOCK_FREE`]
+      [Indicate whether `atomic_flag` is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_BOOL_LOCK_FREE`]
+      [Indicate whether `atomic<bool>` is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_CHAR_LOCK_FREE`]
+      [Indicate whether `atomic<char>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_CHAR16_T_LOCK_FREE`]
+      [Indicate whether `atomic<char16_t>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_CHAR32_T_LOCK_FREE`]
+      [Indicate whether `atomic<char32_t>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_WCHAR_T_LOCK_FREE`]
+      [Indicate whether `atomic<wchar_t>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_SHORT_LOCK_FREE`]
+      [Indicate whether `atomic<short>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_INT_LOCK_FREE`]
+      [Indicate whether `atomic<int>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_LONG_LOCK_FREE`]
+      [Indicate whether `atomic<long>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_LLONG_LOCK_FREE`]
+      [Indicate whether `atomic<long long>` (including signed/unsigned variants) is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_ADDRESS_LOCK_FREE` or `BOOST_ATOMIC_POINTER_LOCK_FREE`]
+      [Indicate whether `atomic<T *>` is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_THREAD_FENCE`]
+      [Indicate whether `atomic_thread_fence` function is lock-free]
+    ]
+    [
+      [`BOOST_ATOMIC_SIGNAL_FENCE`]
+      [Indicate whether `atomic_signal_fence` function is lock-free]
+    ]
+]
+
+In addition to these standard macros, [*Boost.Atomic] also defines a number of extension macros,
+which can also be useful. Like the standard ones, these macros are defined to values `0`, `1` and `2`
+to indicate whether the corresponding operations are lock-free or not.
+
+[table
+    [[Macro] [Description]]
+    [
+      [`BOOST_ATOMIC_INT8_LOCK_FREE`]
+      [Indicate whether `atomic<int8_type>` is lock-free.]
+    ]
+    [
+      [`BOOST_ATOMIC_INT16_LOCK_FREE`]
+      [Indicate whether `atomic<int16_type>` is lock-free.]
+    ]
+    [
+      [`BOOST_ATOMIC_INT32_LOCK_FREE`]
+      [Indicate whether `atomic<int32_type>` is lock-free.]
+    ]
+    [
+      [`BOOST_ATOMIC_INT64_LOCK_FREE`]
+      [Indicate whether `atomic<int64_type>` is lock-free.]
+    ]
+    [
+      [`BOOST_ATOMIC_INT128_LOCK_FREE`]
+      [Indicate whether `atomic<int128_type>` is lock-free.]
+    ]
+    [
+      [`BOOST_ATOMIC_NO_ATOMIC_FLAG_INIT`]
+      [Defined after including `atomic_flag.hpp`, if the implementation
+      does not support the `BOOST_ATOMIC_FLAG_INIT` macro for static
+      initialization of `atomic_flag`. This macro is typically defined
+      for pre-C++11 compilers.]
+    ]
+]
+
+In the table above, `intN_type` is a type that fits storage of contiguous `N` bits, suitably aligned for atomic operations.
+
+[endsect]
+
+[endsect]
+
+[section:usage_examples Usage examples]
+
+[include examples.qbk]
+
+[endsect]
+
+[/
+[section:platform_support Implementing support for additional platforms]
+
+[include platform.qbk]
+
+[endsect]
+]
+
+[/ [xinclude autodoc.xml] ]
+
+[section:limitations Limitations]
+
+While [*Boost.Atomic] strives to implement the atomic operations
+from C++11 as faithfully as possible, there are a few
+limitations that cannot be lifted without compiler support:
+
+* [*Using non-POD-classes as template parameter to `atomic<T>` results
+  in undefined behavior]: This means that any class containing a
+  constructor, destructor, virtual methods or access control
+  specifications is not a valid argument in C++98. C++11 relaxes
+  this slightly by allowing "trivial" classes containing only
+  empty constructors. [*Advise]: Use only POD types.
+* [*C++98 compilers may transform computation- to control-dependency]:
+  Crucially, `memory_order_consume` only affects computationally-dependent
+  operations, but in general there is nothing preventing a compiler
+  from transforming a computation dependency into a control dependency.
+  A C++11 compiler would be forbidden from such a transformation.
+  [*Advise]: Use `memory_order_consume` only in conjunction with
+  pointer values, as the compiler cannot speculate and transform
+  these into control dependencies.
+* [*Fence operations enforce "too strong" compiler ordering]:
+  Semantically, `memory_order_acquire`/`memory_order_consume`
+  and `memory_order_release` need to restrain reordering of
+  memory operations only in one direction. Since there is no
+  way to express this constraint to the compiler, these act
+  as "full compiler barriers" in this implementation. In corner
+  cases this may result in a less efficient code than a C++11 compiler
+  could generate.
+* [*No interprocess fallback]: using `atomic<T>` in shared memory only works
+  correctly, if `atomic<T>::is_lock_free() == true`.
+
+[endsect]
+
+[section:porting Porting]
+
+[section:unit_tests Unit tests]
+
+[*Boost.Atomic] provides a unit test suite to verify that the
+implementation behaves as expected:
+
+* [*fallback_api.cpp] verifies that the fallback-to-locking aspect
+  of [*Boost.Atomic] compiles and has correct value semantics.
+* [*native_api.cpp] verifies that all atomic operations have correct
+  value semantics (e.g. "fetch_add" really adds the desired value,
+  returning the previous). It is a rough "smoke-test" to help weed
+  out the most obvious mistakes (for example width overflow,
+  signed/unsigned extension, ...).
+* [*lockfree.cpp] verifies that the [*BOOST_ATOMIC_*_LOCKFREE] macros
+  are set properly according to the expectations for a given
+  platform, and that they match up with the [*is_lock_free] member
+  functions of the [*atomic] object instances.
+* [*atomicity.cpp] lets two threads race against each other modifying
+  a shared variable, verifying that the operations behave atomic
+  as appropriate. By nature, this test is necessarily stochastic, and
+  the test self-calibrates to yield 99% confidence that a
+  positive result indicates absence of an error. This test is
+  very useful on uni-processor systems with preemption already.
+* [*ordering.cpp] lets two threads race against each other accessing
+  multiple shared variables, verifying that the operations
+  exhibit the expected ordering behavior. By nature, this test is
+  necessarily stochastic, and the test attempts to self-calibrate to
+  yield 99% confidence that a positive result indicates absence
+  of an error. This only works on true multi-processor (or multi-core)
+  systems. It does not yield any result on uni-processor systems
+  or emulators (due to there being no observable reordering even
+  the order=relaxed case) and will report that fact.
+
+[endsect]
+
+[section:tested_compilers Tested compilers]
+
+[*Boost.Atomic] has been tested on and is known to work on
+the following compilers/platforms:
+
+* gcc 4.x: i386, x86_64, ppc32, ppc64, sparcv9, armv6, alpha
+* Visual Studio Express 2008/Windows XP, x86, x64, ARM
+
+[endsect]
+
+[section:acknowledgements Acknowledgements]
+
+* Adam Wulkiewicz created the logo used on the [@https://github.com/boostorg/atomic GitHub project page]. The logo was taken from his [@https://github.com/awulkiew/boost-logos collection] of Boost logos.
+
+[endsect]
+
+[endsect]
diff --git a/3rdParty/Boost/src/libs/atomic/doc/examples.qbk b/3rdParty/Boost/src/libs/atomic/doc/examples.qbk
new file mode 100644
index 0000000..e34c402
--- /dev/null
+++ b/3rdParty/Boost/src/libs/atomic/doc/examples.qbk
@@ -0,0 +1,398 @@
+[/
+ / Copyright (c) 2009 Helge Bahmann
+ /
+ / Distributed under the Boost Software License, Version 1.0. (See accompanying
+ / file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
+ /]
+
+[section:example_reference_counters Reference counting]
+
+The purpose of a ['reference counter] is to count the number
+of pointers to an object. The object can be destroyed as
+soon as the reference counter reaches zero.
+
+[section Implementation]
+
+[c++]
+
+  #include <boost/intrusive_ptr.hpp>
+  #include <boost/atomic.hpp>
+
+  class X {
+  public:
+    typedef boost::intrusive_ptr<X> pointer;
+    X() : refcount_(0) {}
+
+  private:
+    mutable boost::atomic<int> refcount_;
+    friend void intrusive_ptr_add_ref(const X * x)
+    {
+      x->refcount_.fetch_add(1, boost::memory_order_relaxed);
+    }
+    friend void intrusive_ptr_release(const X * x)
+    {
+      if (x->refcount_.fetch_sub(1, boost::memory_order_release) == 1) {
+        boost::atomic_thread_fence(boost::memory_order_acquire);
+        delete x;
+      }
+    }
+  };
+
+[endsect]
+
+[section Usage]
+
+[c++]
+
+  X::pointer x = new X;
+
+[endsect]
+
+[section Discussion]
+
+Increasing the reference counter can always be done with
+[^memory_order_relaxed]: New references to an object can only
+be formed from an existing reference, and passing an existing
+reference from one thread to another must already provide any
+required synchronization.
+
+It is important to enforce any possible access to the object in
+one thread (through an existing reference) to ['happen before]
+deleting the object in a different thread. This is achieved
+by a "release" operation after dropping a reference (any
+access to the object through this reference must obviously
+happened before), and an "acquire" operation before
+deleting the object.
+
+It would be possible to use [^memory_order_acq_rel] for the
+[^fetch_sub] operation, but this results in unneeded "acquire"
+operations when the reference counter does not yet reach zero
+and may impose a performance penalty.
+
+[endsect]
+
+[endsect]
+
+[section:example_spinlock Spinlock]
+
+The purpose of a ['spin lock] is to prevent multiple threads
+from concurrently accessing a shared data structure. In contrast
+to a mutex, threads will busy-wait and waste CPU cycles instead
+of yielding the CPU to another thread. ['Do not use spinlocks
+unless you are certain that you understand the consequences.]
+
+[section Implementation]
+
+[c++]
+
+  #include <boost/atomic.hpp>
+
+  class spinlock {
+  private:
+    typedef enum {Locked, Unlocked} LockState;
+    boost::atomic<LockState> state_;
+
+  public:
+    spinlock() : state_(Unlocked) {}
+
+    void lock()
+    {
+      while (state_.exchange(Locked, boost::memory_order_acquire) == Locked) {
+        /* busy-wait */
+      }
+    }
+    void unlock()
+    {
+      state_.store(Unlocked, boost::memory_order_release);
+    }
+  };
+
+[endsect]
+
+[section Usage]
+
+[c++]
+
+  spinlock s;
+
+  s.lock();
+  // access data structure here
+  s.unlock();
+
+[endsect]
+
+[section Discussion]
+
+The purpose of the spinlock is to make sure that one access
+to the shared data structure always strictly "happens before"
+another. The usage of acquire/release in lock/unlock is required
+and sufficient to guarantee this ordering.
+
+It would be correct to write the "lock" operation in the following
+way:
+
+[c++]
+
+  lock()
+  {
+    while (state_.exchange(Locked, boost::memory_order_relaxed) == Locked) {
+      /* busy-wait */
+    }
+    atomic_thread_fence(boost::memory_order_acquire);
+  }
+
+This "optimization" is however a) useless and b) may in fact hurt:
+a) Since the thread will be busily spinning on a blocked spinlock,
+it does not matter if it will waste the CPU cycles with just
+"exchange" operations or with both useless "exchange" and "acquire"
+operations. b) A tight "exchange" loop without any
+memory-synchronizing instruction introduced through an "acquire"
+operation will on some systems monopolize the memory subsystem
+and degrade the performance of other system components.
+
+[endsect]
+
+[endsect]
+
+[section:singleton Singleton with double-checked locking pattern]
+
+The purpose of the ['Singleton with double-checked locking pattern] is to ensure
+that at most one instance of a particular object is created.
+If one instance has been created already, access to the existing
+object should be as light-weight as possible.
+
+[section Implementation]
+
+[c++]
+
+  #include <boost/atomic.hpp>
+  #include <boost/thread/mutex.hpp>
+
+  class X {
+  public:
+    static X * instance()
+    {
+      X * tmp = instance_.load(boost::memory_order_consume);
+      if (!tmp) {
+        boost::mutex::scoped_lock guard(instantiation_mutex);
+        tmp = instance_.load(boost::memory_order_consume);
+        if (!tmp) {
+          tmp = new X;
+          instance_.store(tmp, boost::memory_order_release);
+        }
+      }
+      return tmp;
+    }
+  private:
+    static boost::atomic<X *> instance_;
+    static boost::mutex instantiation_mutex;
+  };
+
+  boost::atomic<X *> X::instance_(0);
+
+[endsect]
+
+[section Usage]
+
+[c++]
+
+  X * x = X::instance();
+  // dereference x
+
+[endsect]
+
+[section Discussion]
+
+The mutex makes sure that only one instance of the object is
+ever created. The [^instance] method must make sure that any
+dereference of the object strictly "happens after" creating
+the instance in another thread. The use of [^memory_order_release]
+after creating and initializing the object and [^memory_order_consume]
+before dereferencing the object provides this guarantee.
+
+It would be permissible to use [^memory_order_acquire] instead of
+[^memory_order_consume], but this provides a stronger guarantee
+than is required since only operations depending on the value of
+the pointer need to be ordered.
+
+[endsect]
+
+[endsect]
+
+[section:example_ringbuffer Wait-free ring buffer]
+
+A ['wait-free ring buffer] provides a mechanism for relaying objects
+from one single "producer" thread to one single "consumer" thread without
+any locks. The operations on this data structure are "wait-free" which
+means that each operation finishes within a constant number of steps.
+This makes this data structure suitable for use in hard real-time systems
+or for communication with interrupt/signal handlers.
+
+[section Implementation]
+
+[c++]
+
+  #include <boost/atomic.hpp>
+
+  template<typename T, size_t Size>
+  class ringbuffer {
+  public:
+    ringbuffer() : head_(0), tail_(0) {}
+
+    bool push(const T & value)
+    {
+      size_t head = head_.load(boost::memory_order_relaxed);
+      size_t next_head = next(head);
+      if (next_head == tail_.load(boost::memory_order_acquire))
+        return false;
+      ring_[head] = value;
+      head_.store(next_head, boost::memory_order_release);
+      return true;
+    }
+    bool pop(T & value)
+    {
+      size_t tail = tail_.load(boost::memory_order_relaxed);
+      if (tail == head_.load(boost::memory_order_acquire))
+        return false;
+      value = ring_[tail];
+      tail_.store(next(tail), boost::memory_order_release);
+      return true;
+    }
+  private:
+    size_t next(size_t current)
+    {
+      return (current + 1) % Size;
+    }
+    T ring_[Size];
+    boost::atomic<size_t> head_, tail_;
+  };
+
+[endsect]
+
+[section Usage]
+
+[c++]
+
+  ringbuffer<int, 32> r;
+
+  // try to insert an element
+  if (r.push(42)) { /* succeeded */ }
+  else { /* buffer full */ }
+
+  // try to retrieve an element
+  int value;
+  if (r.pop(value)) { /* succeeded */ }
+  else { /* buffer empty */ }
+
+[endsect]
+
+[section Discussion]
+
+The implementation makes sure that the ring indices do
+not "lap-around" each other to ensure that no elements
+are either lost or read twice.
+
+Furthermore it must guarantee that read-access to a
+particular object in [^pop] "happens after" it has been
+written in [^push]. This is achieved by writing [^head_ ]
+with "release" and reading it with "acquire". Conversely
+the implementation also ensures that read access to
+a particular ring element "happens before" before
+rewriting this element with a new value by accessing [^tail_]
+with appropriate ordering constraints.
+
+[endsect]
+
+[endsect]
+
+[section:mp_queue Wait-free multi-producer queue]
+
+The purpose of the ['wait-free multi-producer queue] is to allow
+an arbitrary number of producers to enqueue objects which are
+retrieved and processed in FIFO order by a single consumer.
+
+[section Implementation]
+
+[c++]
+
+  template<typename T>
+  class waitfree_queue {
+  public:
+    struct node {
+      T data;
+      node * next;
+    };
+    void push(const T &data)
+    {
+      node * n = new node;
+      n->data = data;
+      node * stale_head = head_.load(boost::memory_order_relaxed);
+      do {
+        n->next = stale_head;
+      } while (!head_.compare_exchange_weak(stale_head, n, boost::memory_order_release));
+    }
+
+    node * pop_all(void)
+    {
+      T * last = pop_all_reverse(), * first = 0;
+      while(last) {
+        T * tmp = last;
+        last = last->next;
+        tmp->next = first;
+        first = tmp;
+      }
+      return first;
+    }
+
+    waitfree_queue() : head_(0) {}
+
+    // alternative interface if ordering is of no importance
+    node * pop_all_reverse(void)
+    {
+      return head_.exchange(0, boost::memory_order_consume);
+    }
+  private:
+    boost::atomic<node *> head_;
+  };
+
+[endsect]
+
+[section Usage]
+
+[c++]
+
+  waitfree_queue<int> q;
+
+  // insert elements
+  q.push(42);
+  q.push(2);
+
+  // pop elements
+  waitfree_queue<int>::node * x = q.pop_all()
+  while(x) {
+    X * tmp = x;
+    x = x->next;
+    // process tmp->data, probably delete it afterwards
+    delete tmp;
+  }
+
+[endsect]
+
+[section Discussion]
+
+The implementation guarantees that all objects enqueued are
+processed in the order they were enqueued by building a singly-linked
+list of object in reverse processing order. The queue is atomically
+emptied by the consumer and brought into correct order.
+
+It must be guaranteed that any access to an object to be enqueued
+by the producer "happens before" any access by the consumer. This
+is assured by inserting objects into the list with ['release] and
+dequeuing them with ['consume] memory order. It is not
+necessary to use ['acquire] memory order in [^waitfree_queue::pop_all]
+because all operations involved depend on the value of
+the atomic pointer through dereference
+
+[endsect]
+
+[endsect]
diff --git a/3rdParty/Boost/src/libs/atomic/doc/logo.png b/3rdParty/Boost/src/libs/atomic/doc/logo.png
new file mode 100644
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+           x="112.74373"
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+      </text>
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diff --git a/3rdParty/Boost/src/libs/atomic/doc/platform.qbk b/3rdParty/Boost/src/libs/atomic/doc/platform.qbk
new file mode 100644
index 0000000..6b9a9ec
--- /dev/null
+++ b/3rdParty/Boost/src/libs/atomic/doc/platform.qbk
@@ -0,0 +1,312 @@
+[/
+ / Copyright (c) 2009 Helge Bahmann
+ /
+ / Distributed under the Boost Software License, Version 1.0. (See accompanying
+ / file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
+ /]
+
+[section:template_organization Organization of class template layers]
+
+The implementation uses multiple layers of template classes that
+inherit from the next lower level each and refine or adapt the respective
+underlying class:
+
+* [^boost::atomic<T>] is the topmost-level, providing
+  the external interface. Implementation-wise, it does not add anything
+  (except for hiding copy constructor and assignment operator).
+
+* [^boost::detail::atomic::internal_atomic&<T,S=sizeof(T),I=is_integral_type<T> >]:
+  This layer is mainly responsible for providing the overloaded operators
+  mapping to API member functions (e.g. [^+=] to [^fetch_add]).
+  The defaulted template parameter [^I] allows
+  to expose the correct API functions (via partial template
+  specialization): For non-integral types, it only
+  publishes the various [^exchange] functions
+  as well as load and store, for integral types it
+  additionally exports arithmetic and logic operations.
+  [br]
+  Depending on whether the given type is integral, it
+  inherits from either [^boost::detail::atomic::platform_atomic<T,S=sizeof(T)>]
+  or [^boost::detail::atomic::platform_atomic_integral<T,S=sizeof(T)>].
+  There is however some special-casing: for non-integral types
+  of size 1, 2, 4 or 8, it will coerce the datatype into an integer representation
+  and delegate to [^boost::detail::atomic::platform_atomic_integral<T,S=sizeof(T)>]
+  -- the rationale is that platform implementors only need to provide
+  integer-type operations.
+
+* [^boost::detail::atomic::platform_atomic_integral<T,S=sizeof(T)>]
+  must provide the full set of operations for an integral type T
+  (i.e. [^load], [^store], [^exchange],
+  [^compare_exchange_weak], [^compare_exchange_strong],
+  [^fetch_add], [^fetch_sub], [^fetch_and],
+  [^fetch_or], [^fetch_xor], [^is_lock_free]).
+  The default implementation uses locking to emulate atomic operations, so
+  this is the level at which implementors should provide template specializations
+  to add support for platform-specific atomic operations.
+  [br]
+  The two separate template parameters allow separate specialization
+  on size and type (which, with fixed size, cannot
+  specify more than signedness/unsignedness). The rationale is that
+  most platform-specific atomic operations usually depend only on the
+  operand size, so that common implementations for signed/unsigned
+  types are possible. Signedness allows to properly to choose sign-extending
+  instructions for the [^load] operation, avoiding later
+  conversion. The expectation is that in most implementations this will
+  be a normal assignment in C, possibly accompanied by memory
+  fences, so that the compiler can automatically choose the correct
+  instruction.
+
+* At the lowest level, [^boost::detail::atomic::platform_atomic<T,S=sizeof(T)>]
+  provides the most basic atomic operations ([^load], [^store],
+  [^exchange], [^compare_exchange_weak],
+  [^compare_exchange_strong]) for arbitrarily generic data types.
+  The default implementation uses locking as a fallback mechanism.
+  Implementors generally do not have to specialize at this level
+  (since these will not be used for the common integral type sizes
+  of 1, 2, 4 and 8 bytes), but if s/he can if s/he so wishes to
+  provide truly atomic operations for "odd" data type sizes.
+  Some amount of care must be taken as the "raw" data type
+  passed in from the user through [^boost::atomic<T>]
+  is visible here -- it thus needs to be type-punned or otherwise
+  manipulated byte-by-byte to avoid using overloaded assignment,
+  comparison operators and copy constructors.
+
+[endsect]
+
+
+[section:platform_atomic_implementation Implementing platform-specific atomic operations]
+
+In principle implementors are responsible for providing the
+full range of named member functions of an atomic object
+(i.e. [^load], [^store], [^exchange],
+[^compare_exchange_weak], [^compare_exchange_strong],
+[^fetch_add], [^fetch_sub], [^fetch_and],
+[^fetch_or], [^fetch_xor], [^is_lock_free]).
+These must be implemented as partial template specializations for
+[^boost::detail::atomic::platform_atomic_integral<T,S=sizeof(T)>]:
+
+[c++]
+
+  template<typename T>
+  class platform_atomic_integral<T, 4>
+  {
+  public:
+    explicit platform_atomic_integral(T v) : i(v) {}
+    platform_atomic_integral(void) {}
+
+    T load(memory_order order=memory_order_seq_cst) const volatile
+    {
+      // platform-specific code
+    }
+    void store(T v, memory_order order=memory_order_seq_cst) volatile
+    {
+      // platform-specific code
+    }
+
+  private:
+    volatile T i;
+  };
+
+As noted above, it will usually suffice to specialize on the second
+template argument, indicating the size of the data type in bytes.
+
+[section:automatic_buildup Templates for automatic build-up]
+
+Often only a portion of the required operations can be
+usefully mapped to machine instructions. Several helper template
+classes are provided that can automatically synthesize missing methods to
+complete an implementation.
+
+At the minimum, an implementor must provide the
+[^load], [^store],
+[^compare_exchange_weak] and
+[^is_lock_free] methods:
+
+[c++]
+
+  template<typename T>
+  class my_atomic_32 {
+  public:
+    my_atomic_32() {}
+    my_atomic_32(T initial_value) : value(initial_value) {}
+
+    T load(memory_order order=memory_order_seq_cst) volatile const
+    {
+      // platform-specific code
+    }
+    void store(T new_value, memory_order order=memory_order_seq_cst) volatile
+    {
+      // platform-specific code
+    }
+    bool compare_exchange_weak(T &expected, T desired,
+      memory_order success_order,
+      memory_order_failure_order) volatile
+    {
+      // platform-specific code
+    }
+    bool is_lock_free() const volatile {return true;}
+  protected:
+  // typedef is required for classes inheriting from this
+    typedef T integral_type;
+  private:
+    T value;
+  };
+
+The template [^boost::detail::atomic::build_atomic_from_minimal]
+can then take care of the rest:
+
+[c++]
+
+  template<typename T>
+  class platform_atomic_integral<T, 4>
+    : public boost::detail::atomic::build_atomic_from_minimal<my_atomic_32<T> >
+  {
+  public:
+    typedef build_atomic_from_minimal<my_atomic_32<T> > super;
+
+    explicit platform_atomic_integral(T v) : super(v) {}
+    platform_atomic_integral(void) {}
+  };
+
+There are several helper classes to assist in building "complete"
+atomic implementations from different starting points:
+
+* [^build_atomic_from_minimal] requires
+  * [^load]
+  * [^store]
+  * [^compare_exchange_weak] (4-operand version)
+
+* [^build_atomic_from_exchange] requires
+  * [^load]
+  * [^store]
+  * [^compare_exchange_weak] (4-operand version)
+  * [^compare_exchange_strong] (4-operand version)
+  * [^exchange]
+
+* [^build_atomic_from_add] requires
+  * [^load]
+  * [^store]
+  * [^compare_exchange_weak] (4-operand version)
+  * [^compare_exchange_strong] (4-operand version)
+  * [^exchange]
+  * [^fetch_add]
+
+* [^build_atomic_from_typical] (<I>supported on gcc only</I>) requires
+  * [^load]
+  * [^store]
+  * [^compare_exchange_weak] (4-operand version)
+  * [^compare_exchange_strong] (4-operand version)
+  * [^exchange]
+  * [^fetch_add_var] (protected method)
+  * [^fetch_inc] (protected method)
+  * [^fetch_dec] (protected method)
+
+  This will generate a [^fetch_add] method
+  that calls [^fetch_inc]/[^fetch_dec]
+  when the given parameter is a compile-time constant
+  equal to +1 or -1 respectively, and [^fetch_add_var]
+  in all other cases. This provides a mechanism for
+  optimizing the extremely common case of an atomic
+  variable being used as a counter.
+
+  The prototypes for these methods to be implemented is:
+  [c++]
+
+    template<typename T>
+    class my_atomic {
+    public:
+      T fetch_inc(memory_order order) volatile;
+      T fetch_dec(memory_order order) volatile;
+      T fetch_add_var(T counter, memory_order order) volatile;
+    };
+
+These helper templates are defined in [^boost/atomic/detail/builder.hpp].
+
+[endsect]
+
+[section:automatic_buildup_small Build sub-word-sized atomic data types]
+
+There is one other helper template that can build sub-word-sized
+atomic data types even though the underlying architecture allows
+only word-sized atomic operations:
+
+[c++]
+
+  template<typename T>
+  class platform_atomic_integral<T, 1> :
+    public build_atomic_from_larger_type<my_atomic_32<uint32_t>, T>
+  {
+  public:
+    typedef build_atomic_from_larger_type<my_atomic_32<uint32_t>, T> super;
+
+    explicit platform_atomic_integral(T v) : super(v) {}
+    platform_atomic_integral(void) {}
+  };
+
+The above would create an atomic data type of 1 byte size, and
+use masking and shifts to map it to 32-bit atomic operations.
+The base type must implement [^load], [^store]
+and [^compare_exchange_weak] for this to work.
+
+[endsect]
+
+[section:other_sizes Atomic data types for unusual object sizes]
+
+In unusual circumstances, an implementor may also opt to specialize
+[^public boost::detail::atomic::platform_atomic<T,S=sizeof(T)>]
+to provide support for atomic objects not fitting an integral size.
+If you do that, keep the following things in mind:
+
+* There is no reason to ever do this for object sizes
+  of 1, 2, 4 and 8
+* Only the following methods need to be implemented:
+  * [^load]
+  * [^store]
+  * [^compare_exchange_weak] (4-operand version)
+  * [^compare_exchange_strong] (4-operand version)
+  * [^exchange]
+
+The type of the data to be stored in the atomic
+variable (template parameter [^T])
+is exposed to this class, and the type may have
+overloaded assignment and comparison operators --
+using these overloaded operators however will result
+in an error. The implementor is responsible for
+accessing the objects in a way that does not
+invoke either of these operators (using e.g.
+[^memcpy] or type-casts).
+
+[endsect]
+
+[endsect]
+
+[section:platform_atomic_fences Fences]
+
+Platform implementors need to provide a function performing
+the action required for [funcref boost::atomic_thread_fence atomic_thread_fence]
+(the fallback implementation will just perform an atomic operation
+on an integer object). This is achieved by specializing the
+[^boost::detail::atomic::platform_atomic_thread_fence] template
+function in the following way:
+
+[c++]
+
+  template<>
+  void platform_atomic_thread_fence(memory_order order)
+  {
+    // platform-specific code here
+  }
+
+[endsect]
+
+[section:platform_atomic_puttogether Putting it altogether]
+
+The template specializations should be put into a header file
+in the [^boost/atomic/detail] directory, preferably
+specifying supported compiler and architecture in its name.
+
+The file [^boost/atomic/detail/platform.hpp] must
+subsequently be modified to conditionally include the new
+header.
+
+[endsect]
author	Tobias Markmann <tm@ayena.de>	2016-04-05 13:17:19 (GMT)
committer	Tobias Markmann <tm@ayena.de>	2016-04-05 19:42:39 (GMT)
commit	2b560b129b7a31fc8cc07f618e763c95a22bf832 (patch)
tree	73e72cdc758b79d01485dc28dcedd48b26859ae8 /3rdParty/Boost/src/libs/atomic/doc
parent	3c560e31b0f168da917e8d566db01fd1cd997d86 (diff)
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